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a
IMVP-II-Compliant Core Power Controller for Mobile CPUs ADP3422
FUNCTIONAL BLOCK DIAGRAM
VCC
FEATURES Certified IMVP-II Controller Excellent Transient Containment Minimum Number of Output Capacitors Fast, Smooth, Output Transition During VID Code Change Current Limit with Hiccup Protection Transient-Glitch-Free Power Good Low Shutdown Current Soft Start Eliminates In-Rush Current Surge Adaptive Noise-Blanking Enhancement for Speed and Stability Highly Redundant Over-Voltage and Reverse-Voltage Protection Controls Synchronous Rectifier for Improved Battery Life APPLICATIONS IMVP-II Enabled Core DC/DC Converters Fixed-Voltage Mobile CPU Core DC/DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies
ADP3422
HYSSET CPUSET FSHIFT DSHIFT BSHIFT HYSTERESIS AND SHIFT-SETTING VR
CS+ CLIM CS- VID4 VID3 VID2 VID1 VID0 DACOUT SWFB VR VCC PROGRAMMED DAC AND FIXED REFERENCE EN CORE REG OUT RAMP
GENERAL DESCRIPTION
The ADP3422 is a hysteretic dc-dc buck converter controller to power a mobile processor's core. The optimized low voltage design is powered from the 3.3 V system supply. The output voltage is set by a 5-bit VID code. To accommodate the transition time required by the newest processors for on-the-fly VID changes, the ADP3422 features high-speed operation to allow a minimized inductor size that results in the fastest change of current to the output. To further allow for the minimum number of output capacitors to be used, the ADP3422 features active voltage positioning that can be optimally compensated to ensure a superior load transient response. The output signal interfaces with the ADP3415 MOSFET driver that is optimized for high speed and high efficiency for driving both the upper and lower (synchronous) MOSFETs of the buck converter.
BOM DSLP DPRSLP PWRGD SD
UVLO AND MAIN BIAS PWRGD BLANKER OP MODE SELECTOR
SR CONTROL COREFB PWRGD MONITOR SS DRVLSD CLAMP
SS-HICCUP TIMER AND OCP OVP AND RVP
POWER MANAGEMENT
GND
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
BOMSEL DSLPSEL
ADP3422-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS1 (0 T 85 C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
Parameter SUPPLY-UVLO-SHUTDOWN Normal Supply Current UVLO Supply Current Shutdown Supply Current UVLO Threshold Symbol ICC ICC(UVLO) ICCSD VCCH VCCL VCCHYS VSDTH VCOREFBH Conditions Min Typ 6 SD = L VCC Rising Up, VSS = 0 V VCC Falling, VSS Floating 1 2.95 2.7 50 VCC/2 0.9 V < VDAC < 1.675 V VCOREFB Rising VCOREFB Falling VCOREFB Rising VCOREFB Falling VCOREFB = VDACOUT VCOREFB = 0.8 VDACOUT VCC = 3.3 V VSS = 0.5 V VSS = 0.5 V, VCC = 2.5 V VREG = 1.25 V, VRAMP = VCOREFB = 1.27 V VSS Falling VSS Rising VRAMP = VCOREFB = 1.27 V VSS Rising VSS Falling 0.8 10 0.600 -0.85 1.3 VREG = 1.25 V VREG = VRAMP = 1.25 V VCC = 3.0 V VCC = 3.6 V 1.5 0.3 2.5 0 50 3 3 75 140 VCC/2 3.0 0.4 10 10
A COREFB = VDAC ( VDACOUT), VREG = VCS- = VVID = 1.25 V, VCPUSET = 0 V, ROUT = 100 k , COUT = 10 pF, CSS = 47 nF, RPWRGD = 5 k to VCC, RCLAMP = 5.1 k to VCC, HYSSET, BSHIFT, DSHIFT, and FSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, SWFB = L, unless otherwise noted. Current sunk by a pin has a positive sign, sourced by a pin has a negative sign.)
Max 15 200
Unit mA A A V V mV
UVLO Hysteresis Shutdown Threshold (CMOS Input) POWERGOOD Core Feedback Threshold Voltage
PowerGood Output Voltage (Open Drain Output) Blanking Time SOFT-START/HICCUP TIMER Charge/Discharge Current Soft-Start Enable/Hiccup Termination Threshold
VPWRGD tPWRGD,BLNK2 ISS VSSEN
1.12 VDAC 1.095 VDAC 0.88 VDAC 0.855 VDAC 0.95 VCC 0 100 -16 0.6
1.145 VDAC 1.12 VDAC 0.905 VDAC 0.88 VDAC VCC 0.8
V V V V V V s A A
150 200 2.05 2.0
200
mV mV V V
Soft-Start Termination/Hiccup Enable Threshold VID DAC VID Input Threshold (CMOS Inputs) VID Input Current (Internal Active Pull-up) Output Voltage Output Voltage Accuracy Output Voltage Settling Time3 CORE COMPARATOR Input Offset Voltage Input Bias Current Output Voltage Propagation Delay Time3 Rise and Fall Time2 Blanking Time Switch Feedback Threshold (CMOS Input)
VSSTERM
VVID0...4 IVID0...4 VDAC VDAC/VDAC tDACS4 VCOREOS IREG VOUT_H VOUT_L tRMPOUT_PD5 tOUT_R6 tOUT_F6 tBLNK VSWFB_TH
VID 0...4 = L See VID Code Table 1
0.7 VCC 40 1.750 +0.85
V A V % s mV A V V ns ns ns ns ns V
OUT L-H Transition OUT H-L Transition
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ADP3422
Parameter HYSTERESIS SETTING Hysteresis Current Symbol IRAMP_H Conditions VREG = 1.25 V VCOREFB = VDAC IHYSSET = 0 VRAMP = 1.23 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.27 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.23 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A VRAMP = 1.27 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A Min Typ Max Unit
1 +8 +89 -8 -89 +6.4 +71 -6.4 -71 1.61 -92.5 +10 +100 -10 -100 +8 +80 -8 -80 1.7 -100 +12 +111 -12 -111 +9.6 +89 -9.6 -89 1.79 -107.5
A A A A A A A A A V A V A V A V V V V
Hysteresis Reference Voltage SHIFT SETTING Battery-Shift Current
VHYSSET IRAMPB VBSHIFT IRAMPD VDSHIFT IRAMPF VFSHIFT VBOM VDSLP VDPRSLP VVID = 1.25 V IBSHIFT = -100 A, BOM = L DSLP = H, VCPUSET = 0 V
Battery-Shift Reference Voltage DeepSleep-Shift Current
VVID = 1.25 V -92.5 IDSHIFT = -100 A, BOM = H DSLP = L, VCPUSET = 0 V VVID = 1.25 V IFSHIFT = -100 A, BOM = L DSLP = H, VCPUSET = 2 V -92.5
VDAC -100
-107.5
DeepSleep-Shift Reference Voltage CPU-FID-Shift Current
VDAC -100
-107.5
CPU-FID-Shift Reference Voltage SHIFT CONTROL INPUTS BOM Threshold (CMOS Input) DSLP Threshold (IO-Level CMOS Input) DPRSLP Mode Threshold (CMOS Input) CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Current
VDAC VCC/2 0.9 VCC/2
VCLIMOS ICS+ ICS-
Propagation Delay Time
tCLPD5
VCS- = 1.25 V VCS+ = 1.25 V VCOREFB = VRAMP = 1.23 V VREG = VCS- = 1.25 V IHYSSET = 0 VCS+ = 1.23 V BOM = H IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.27 V, BOM = H IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.23 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A VCS+ = 1.27 V, BOM = L IHYSSET = -10 A IHYSSET = -100 A
0.2 -0.3
6
mV A A A A A A A A A A A ns
-0.6 -27 -270 -18 -180 -21 -226 -14 -144 -31.5 -301.5 -1.5 -21.5 -201.5
-3 -36 -333 -3 -25 -223
-25.5 -30 -241.5 -267 -17.5 -21 -161.5 -179 65
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ADP3422-SPECIFICATIONS (continued)
Parameter
LOW-SIDE DRIVE CONTROL Output Voltage (CMOS Output) Output Current
Symbol
VDRVLSD IDRVLSD
Conditions
DPRSLP = H DPRSLP = L VDRVLSD = 1.5 V DPRSLP = L DPRSLP = H
Min
Typ
Max
0.4 VCC
Unit
V V mA mA
0.7 VCC +0.4 -0.4
OVER/REVERSE VOLTAGE PROTECTION Over-Voltage Threshold Reverse-Voltage Threshold
VCOREFB,OVP VCOREFB,RVP
Output Current (Open Drain Output) ICLAMP
VCOREFB Rising VCOREFB Falling VCOREFB Falling VCOREFB Rising VCLAMP = 1.5 V VCOREFB = 2.2 V VCOREFB = VDACOUT = 1.25 V 1
2.0 1.8 -0.3 -0.05
2.2
V V V V A mA
10 4
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Two test conditions: 1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time. 2. PWRGD is forced to fail (V COREFB,BAD = 1.0 V at V VID = 1.25 V setting) but gets into the CoreGood-window (V COREFB,GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time. 3 Guaranteed by characterization. 4 Measured from 50% of VID code transition amplitude to the point where V DACOUT settles within 1% of its steady state value. 5 40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. 6 Measured between the 30% and 70% points of the output voltage swing. Specifications subject to change without notice.
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ADP3422
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
HYSSET CPUSET FSHIFT DSHIFT BSHIFT VID4 (MSB) VID3 VID2 VID1
1 2 3 4 5 6 7 28 27 26 25 24
Input Supply Voltage (VCC) . . . . . . . . . . . . . . -0.3 V to +7 V UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V All Other Inputs/Outputs . . . . . . . . . -0.3 V to (VCC + 0.3 V) Operating Ambient Temperature Range . . . . . . . 0C to 85C Junction Temperature Range . . . . . . . . . . . . . . . 0C to 150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98C/W Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
CS- CS+ REG RAMP VCC OUT
TOP VIEW 22 GND (Not to Scale) 8 21 DACOUT
9 20 19 18 17 16 15
ADP3422
23
COREFB SS SWFB DRVLSD CLAMP SD
VID0 (LSB) 10 BOM 11
ORDERING GUIDE
DSLP 12 DPRSLP 13
Model ADP3422JRU
Temperature Package Range Description 0C to 85C
Package Option
PWRGD 14
Thin Shrink Small RU-28 Outline (TSSOP)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3422 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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ADP3422
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic HYSSET
Function Hysteresis Set. This is an analog I/O pin whose output is a voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set the hysteretic currents for the Core Comparator and the Current Limit Comparator. Modification of the resistance will affect both the hysteresis of the feedback regulation and the current limit set point and hysteresis. The application circuit suggests a resistor divider, as this pin's functionality is used to supply a divided reference voltage to another high-impedance pin. CPU Set. This is a high-impedance analog input pin to which a reference voltage is applied via a resistor divider (e.g., from the HYSSET pin). The applied reference to this pin sets a threshold that lies between two VID codes, each of which represents the Battery Optimized Mode (BOM) VID code of a certain CPU. At startup of the CPU regulator, the BOM VID code is received and the corresponding DACOUT voltage is compared against the CPUSET voltage. The type of CPU is then categorized as being in one of two frequency categories, the lower of which has a lower BOM VID code. The information is latched into the IC and, if the lower frequency CPU has been detected, is used to add a downward shift of the regulated core voltage to the optimum level. The shift is performed using the FSHIFT and RAMP pins. Frequency Shift. This is an analog I/O pin whose output is a voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the latched function of the CPUSET pin. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to the frequency range of the CPU. Deep Sleep Shift. This is an analog I/O pin whose output is a voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the DSLP signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to Deep Sleep mode of CPU operation. Battery Optimized Mode Shift. This is an analog I/O pin whose output is a voltage reference and whose input is a current that is programmed by an external resistance to ground. The current is used in the IC to set a switched bias current out of the RAMP pin, depending on whether it is activated by the BOM signal. When activated, this added bias current creates a downward shift of the regulated core voltage to a predetermined optimum level for regulation corresponding to Battery Optimized Mode of CPU operation. VID Input. Most significant bit. VID Input VID Input VID Input VID Input. Least significant bit. Battery Optimized Mode (active low). This is a digital input pin coming from a system signal corresponding to Battery Optimized Mode of the CPU operation in its active low state and Performance Optimized Mode (POM) in its disactivated high state. The signal controls the optimal positioning of the core voltage regulation level according to the functionality of the BSHIFT and RAMP pins. It is also used to initiate a blanking period for the PWRGD signal (to disable its response to a pending dynamic core voltage change according to the VID code) whenever a signal transition occurs. Deep Sleep Mode (active low). This is a digital input pin coming from a system signal which, in its active state, corresponds to Deep Sleep mode of the CPU, which is a subset operating mode of either BOM or POM operation. The signal controls the optimal positioning of the core voltage regulation level according to the functionality of the DSHIFT and RAMP pins.
2
CPUSET
3
FSHIFT
4
DSHIFT
5
BSHIFT
6 7 8 9 10 11
VID4 VID3 VID2 VID1 VID0 BOM
12
DSLP
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Pin No. 13 Mnemonic DPRSLP Function Deeper Sleep Mode (active high). This is a digital input pin coming from a system signal corresponding to Deeper Sleep mode of the CPU operation in its active high state. It is used to initiate a blanking period for the PWRGD signal (to disable its response to a pending dynamic core voltage change according to the VID code) whenever a signal transition occurs. Power Good (active high). This is an open drain output pin which, via the assistance of an external pull-up resistor, indicates that the core voltage is within the specified tolerance of the VID programmed value or else in a VID transition state as indicated by a recent state transition of either the BOM or DPRSLP pins. PWRGD is deactivated (pulled low) when the IC is disabled or in UVLO mode or soft-start. The open drain output allows external ORing with other open drain/collector powergood indicators. Shutdown (active low). This is a digital input pin coming from a system signal which, in its active state, shuts down the IC operation, placing the IC in its lowest quiescent current state for maximum power savings. Clamp (active high). This is an open drain output pin which, via the assistance of an external pull-up resistor, indicates that the core voltage should be clamped for its protection. To allow the highest level of protection, the CLAMP signal is developed using both a redundant reference and a redundant feedback path with respect to those of the main regulation loop. It is also latched. In a preferred and more conservative configuration, the core voltage is clamped by an external FET. The initial protection function is served when it is activated by detection of either an overvoltage or a reverse-voltage condition on the COREFB pin. A backup protection function due to loss of the latched signal at IC power-off is served by connecting the pull-up resistor to a system "ALWAYS" regulator output (e.g., V5_ALWAYS). If the external FET is used, this implementation will keep the core voltage clamped until the ADP3422 has power reapplied, thus keeping protection for the CPU even after a hard-failure power-down and restart (e.g., a shorted top FET). Drive-Low Shutdown (active low). This is a digital output pin which, in its active state, indicates that the lower FET of the core VR should be disabled. In the suggested application schematic this pin is directly connected to the pin of the same name on the ADP3415 or other driver IC. The pin is normally asserted in the light load condition, but its assertion will be deactivated by the consideration of a number of dynamic conditions where operation of the lower FET may be needed. Switched Node Feedback. This is a high-impedance analog input pin that is used to allow the ON-time noise blanking function to terminate earlier than its internally preset time by its indication that the turn-ON of the upper FET has occurred. A resistor must be inserted between the pin and the switched node of the core VR so that the input can be clamped (at ~7V) and is not exposed to high voltage. This pin can also be shorted to ground if the need for this speed enhancement is deemed unnecessary. Soft Start. This is an analog I/O pin whose output is a controlled current source used to charge or discharge an external grounded capacitor and whose input is the detected voltage that is indicative of elapsed time. The pin controls the soft start time of the IC as well as the hiccup cycle time during short circuit. Hiccup operation is a feature that was added to reduce short circuit power dissipation by more than an order of magnitude, while still allowing an automatic restart when the short is removed. Core Feedback. This is a high-impedance analog input pin that is used to monitor the output voltage for setting the proper state of the PWRGD and CLAMP pins. It is generally recommended to RC-filter the noise from the monitored core voltage, as suggested by the application schematic. VID-Programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output voltage regulation. Ground Driver Command Output Signal. This is a digital output pin which is used to command the state of the switched node via the driver. It should be connected to the IN pin of the ADP3415 or similar driver. Power Supply
14
PWRGD
15
SD
16
CLAMP
17
DRVLSD
18
SWFB
19
SS
20
COREFB
21 22 23 24
DACOUT GND OUT VCC
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ADP3422
Pin No. 25 Mnemonic RAMP Function Regulation Ramp Feedback Input. This is a high-impedance analog input pin which is used for providing negative feedback of the hysteretically-controlled output. Several switched current sources also appear at this input, most notably the cycle-by-cycle hysteresis-setting switched current programmed by the HYSSET pin. The external resistive termination at this pin sets the magnitude of the hysteresis applied to the regulation loop. Regulation Voltage Summing Input. This is a high-impedance analog input pin into which the voltage reference of the feedback loop allows the summing of both the DACOUT voltage and the core voltage for programming the output resistance of the core voltage regulator. This is also the pin at which an optimized transient response can be tailored using Analog Devices' patented ADOPTTM design technique. Current Limit Positive Sense. This is a high-impedance analog input pin that is normally connected to the positive node of the current sense resistor. Current Limit Negative Sense. This is a high-impedance analog input pin that is normally connected via a current-limit programming resistor to the negative node of the current sense resistor. A hystereticallycontrolled current--three times the current programmed at the HYSSET pin--flows out of this pin and develops a current-limit-setting voltage across that resistor. This voltage must be exceeded by the inductor current generated current sense voltage in order to trigger the current limit function. When it is triggered, the current flowing out of this pin is reduced--to two-thirds of its previous value--producing hysteresis in the current limit operation.
26
REG
27 28
CS+ CS-
ADOPT is a trademark of Analog Devices, Inc.
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Typical Performance Characteristics-ADP3422
10000 NORMAL OPERATING MODE A 1000
100 OUT = HIGH, RHYS = 17k
SUPPLY CURRENT - A
HYSTERESIS CURRENT -
100 UVLO MODE
OUT = HIGH, RHYS = 170k 0 OUT = LOW, RHYS = 170k
10
1 SHUTDOWN MODE 0.1 0 20 40 60 TEMPERATURE - C 80 100
OUT = LOW, RHYS = 17k -100 0 20 40 60 TEMPERATURE - C 80 100
TPC 1. Supply Current vs. Temperature
TPC 4. Core Hysteresis Current vs. Temperature
1.765
+0.85%
0 -50
FULL SCALE
OUT = LOW, RHYSSET = 170k OUT = HIGH, RHYSSET = 170k
CL - PIN CURRENT - A
1.750
-100 -150 -200 -250 -300
DAC OUTPUT - V
1.735 0.605
-0.85%
OUT = LOW, RHYSSET = 17k
+0.85% 0.600 ZERO SCALE -0.85% 0 20 40 60 AMBIENT TEMPERATURE - C 80 100
OUT = HIGH, RHYSSET = 17k 0 20 40 60 TEMPERATURE - C 80 100
0.595
-350
TPC 2. DAC Output Voltage vs. Temperature
TPC 5. Current Limit Programming Current vs. Temperature
100
SOFT-START TIME - ms
-10 -5 5 0 RELATIVE CORE VOLTAGE - % 10 15
HIGH
10
POWER GOOD
1
0.1
LOW -15
0.01 0.1
1 10 TIMING CAPACITANCE - nF
100
TPC 3. Power Good vs. Relative Core Voltage Variation
TPC 6. Soft-Start Time vs. Timing Capacitance
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ADP3422
APPLICATION INFORMATION
VIN Q1 L IL RCS COC CO RC RD VREF RE VOUT LOAD
This application section presents both the theoretical background and the detailed procedure for designing dc/dc converters with the ADP3422 controller for mobile CPUs. The ADP3422 is used in a unique ripple regulator (also called hysteretic regulator) configuration, which allows employing ADOPT, Analog Devices' optimal voltage positioning technique to implement the output desired voltage impedance statically and dynamically, as required by Intel's IMVP-2 specification.
Hysteretic Regulator
Q2
VH
Figure 1 shows the conventional hysteretic regulator and the characteristic waveforms. The operation is as follows. During the time the upper transistor, Q1, is turned on, the inductor current, IL, and also the output voltage, VOUT, increase. When VOUT reaches the upper threshold of the hysteretic comparator, Q1 is turned off, Q2 is turned on, and the inductor current and also the output voltage begin to decrease. The cycle repeats after VOUT reaches the lower threshold of the hysteretic comparator.
VIN VOUT Q1 L VSW Q2 IL CO RE VOUT VSW LOAD IL VH VREF VH
Figure 2. Modified Hysteretic Regulator with ADOPT
The implementation requires adding a resistive divider (RC and RD) between the reference voltage and the output, and connecting the tap of the divider to the noninverting input of the hysteretic comparator. A capacitor, COC, is placed across the upper member (RC) of the divider. It is easily shown that the output impedance of the converter can be no less than the ESR of the output capacitor. A straightforward derivation demonstrates that the output impedance of the converter in Figure 2 can be minimized to equal the ESR, RE, when the following two equations are valid (neglecting PCB trace resistance for now):
RD RE - RCS = RC RCS
(2)
and COC =
2 CO RE RCS RD
Figure 1. Conventional Hysteretic Regulator and Its Characteristic Waveforms
(3)
The switching frequency is determined by the equivalent series resistance RE of the output capacitor, the inductance L of the inductor, the input and output voltages, and the hysteresis VH of the comparator. It is as follows:
From (3), the series resistance is:
f=
RE (VIN - VOUT )VOUT LVH VIN
(1)
Since there is no voltage-error amplifier in the hysteretic regulator, its response to any change in the load current or the input voltage is virtually instantaneous. Therefore, the hysteretic regulator represents the fastest possible dc/dc converter control technique. A slight disadvantage of the hysteretic regulator is that its frequency varies with the input and output voltages. In a typical mobile CPU converter application, the worst-case frequency variation due to the input voltage variation is in the order of 30%, which is usually acceptable. In the simplest implementation of the hysteretic converter, shown in Figure 1, the frequency also varies proportionally with the ESR of the output capacitor. Since the initial value is often poorly controlled, and the ESR of electrolytic capacitors also changes with temperature and age, practical ESR variations can easily lead to a frequency variation on the order of three to one. However, using the ADP3422 controller in a modified hysteretic topology eliminates the dependence of the operating frequency on the ESR. In addition, the modification allows the optimal implementation, ADOPT, of the Intel's IVMP-2 load-line specification. Figure 2 shows the modified hysteretic regulator.
RE R (4) 1+ D RC This is the ADOPT configuration and design procedure that allows the maximum possible ESR to be used while meeting a given load-line specification. RCS =
It can be seen from (4) that unless RD is zero or RC is infinite, RCS will be always smaller than RE. An advantage of the circuit of Figure 2 is that if we select the ratio RD/RC well above unity, the additional dissipation introduced by the series resistance RCS will be negligible. Another interesting feature of the circuit in Figure 2 is that the ac voltage across the two inputs of the hysteretic comparator is now equal only to the ac voltage across RCS. This is due to the presence of the capacitor COC, which effectively couples the ac component of the output voltage to the noninverting input voltage of the comparator. Since the comparator sees only the ac voltage across RCS, in the circuit of Figure 2 the dependence of the switching frequency on the ESR of the output capacitor is completely eliminated. Equation (5) presents the expression for the switching frequency.
f=
RCS (VIN - VOUT )VOUT LVH VIN
(5)
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V_5S D1 BAR43S 7V-21V V_DC C12 0.1 F C1 10 F C2 0.1 F C15 0.1 F C18 10 F C16 0.1 F C17 0.1 F C19 10 F C20 10 F C21 10 F C3 1000pF
ADP3415
1 IN CORE_ON 3 DRVLSD SW 8 GND 7 D3 D2 DRVL 6 4 DLY R7 5 VCC 2 SD DRVH 9 Q1 IR7807V Q2 IR7807V BST 10
C22 10 F
C23 10 F
Q3 IR7811W IR7811W IR7811W
Q4
Q5
V_3S L1 0.66 H R6 2.7 RCL 10pF
RC
Figure 3. Application Circuit
C4 RCSF 10pF C5 COC RD C9 10nF R9 47nF CSS R12 10k C10 V_5 ALWAYS R15 5.1k C24 150 F C25 150 F C26 150 F RA C6 0.1 F C8 1F CCSF CORE_ON Q6 IR7807V
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RSET1
RSET2
ADP3422
1
HYSSET
CS- 28
RFSHIFT
2
CPUSET
CS+ 27
RDSHIFT
3
FSHIFT
REG 26
RCS
RBSHIFT
4
DSHIFT
RAMP 25
5
BSHIFT
VCC 24
VR_VID4
6
VID4
OUT 23
VR_VID3
7
VID3
GND 22
VR_VID2
8
VID2
DACOUT 21
VCORE
VR_VID1
9
VID1
COREFB 20
VR_VID0
10 VID0
SS 19
C27 150 F
C28 150 F
C29 150 F
C30 150 F
C31 150 F
C32 150 F
C33 150 F
GMUXSEL
11 BOM
SWFB 18
DPSLP
12 DSLP
DRVLSD 17
DPRSLPVR
13 DPRSLP
CLAMP 16
14 PWRGD
SD 15
V_3S
R19 5.1k
ADP3422
ADP3422
Application Schematic
Figure 3 shows the simplified application schematic of the ADP3422 control IC. The ADP3422, together with its companion dual MOSFET driver IC, the ADP3415, controls a hysteretic converter that generates the core voltage for the CPU.
Design Procedure--Power Stage Components
The first step of the converter design is to select the MOSFETs to be used based on acceptable dc and switching losses. For this selection, the designer is referred to the MOSFET manufacturers who may provide not only a recommendation for the MOSFETs to be used for the specific application, but also data and/or guidelines for determining an acceptable maximum operating frequency. With this information, the next step is to choose an inductance value--usually the smallest available value, that will yield an acceptable ripple current. A ripple current 30%~60% of the maximum core current is recommended. Inductance, frequency, and ripple current are related by formula (6), derived from (5):
L= 1 (VIM - VVID )VVID f MAX I RPP VIM
The final step in finishing the design of the power stage is selecting the output capacitors. There are two primary considerations in choosing those capacitors. The total ESR may not exceed the output resistance required by Intel's IMVP-2 specification. Also the total capacitance must be checked to make sure that it is sufficient to prevent overshoot beyond the voltage step caused by the ESR during a full load transient, according to the formula:
L x ( IO ( MAX ) - IO ( MIN ) ) (8) ROUT x VL where IO(MIN) is the minimum rated current for the normal operation region of the CPU where IO(MAX) can occur, and VL is the voltage applied across the inductor in order to ramp the current in the direction of the load step. The minimum CPU voltage represents a critical performance limit that must not be violated during a load step increase. Therefore, the minimum capacitance must never be less than the calculated value when using VL = VI(MIN) - VVID in (8) the voltage applied across the inductor to ramp up the current. However, overshoot would still occur unless the capacitance is greater than the calculated value when using VL = VVID in (8). The magnitude of the overshoot is given by: CO ( MIN ) =
VOS = L IRPP 2 2 - IO ( MIN ) + VVID - ROUT IO ( MAX ) - VVID IO ( MAX ) + CO 2
2
(6)
where: L = inductance value fMAX = maximum acceptable switching frequency IRPP = selected peak-to-peak ripple current VIM = maximum input voltage VVID = nominal programmed VID voltage Assuming f MAX = 250 kHz, I RPP = 8 A, V IM = 20 V, and VVID = 1.25 V, the required inductance value is L = 729 nH. A standard value of 660 nH is available. The next step is to select the current sensing resistor, RCS. The restrictions are that (1) the resistance should not be higher than the core converter output impedance defined by Intel's IMVP-2 specification, and (2) the resistance should not be so low that the errors in reading the current sense signal become a problem. The IMVP-2 specification requires that the converter output impedance, ROUT, be 4 m. An RCS value of above one-quarter of the nominal output impedance provides sufficient protection against errors in the current sense signal. The chosen value is RCS = 1.5 m. Also, the power dissipation, PCS, should be calculated to ensure that a properly sized resistor is selected:
2 PCS = RCS IO ( MAX )
[
]
(9)
For this design example, output capacitors with a capacitance of 150 F and a maximum ESR of 20 m are chosen. Given the target of ROUT = 4 m, five capacitors would be needed to achieve a total ESR of not more than 4 m. The total capacitance of five of these capacitors is 750 F. This capacitance is greater than the value required for a load step increase, even for an input voltage as low as 6 V; but it is less than what is needed to prevent an overshoot for a load step decrease, where only the output voltage is applied across the inductor to ramp down the current to the minimum value. Assuming that the minimum current is zero, the overshoot above VVID is 89 mV.
Design Procedure--Control Circuit Components
The output resistance is implemented by using the proper ratio of two resistors, which connect to the REG pin. One resistor, RD, connects to the DAC reference and the other, RC, connects to the core voltage. From (2):
RD RE - RT - RCS = RC RCS
(10)
(7)
where RT is the PCB trace resistance between the current sense resistor and the CPU measurement point. There is no inherent restriction on the absolute value of either RD or RC, but values in the single k range are recommended. These resistors can now be selected.
where IO(MAX) is the maximum output current. In this design example IO(MAX) = 19 A. The resulting dissipation of the current sense resistor is 542 mW.
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A capacitor is required across RC to achieve optimal compensation. This ensures that the output voltage does not bounce back temporarily right after a load transient, i.e., the output impedance of the converter is purely resistive. The bounce-back is undesirable because it increases the peak-to-peak deviation in the output voltage. From (3), the optimal capacitance value is:
COC = CO RE RC RD
The second shift is for optimizing the output voltage when the Deep Sleep operating mode is selected in conjunction with either the POM or BOM VID codes. This shift is achieved by connecting a resistor, RDSHIFT, between the DSHIFT pin and ground. The shift will be used whenever the DPSLP pin is driven low. The shift is given by:
VDSHIFT = R VVID , BOM 1 + D RDSHIFT RC - RA
(11)
(15)
At this point, the exact COC value should be selected as close to the calculated one as possible. It is generally recommended to choose the nearest value of COC which is not greater than what is calculated. Optionally, COC can be chosen first arbitrarily and the values of RD and RC can be reselected to satisfy the previous two equations. The output impedance is now set. The next step in the design is to determine the value of the hysteresis-setting resistor, RA, which sets the inductor ripple current. RA connects between the RAMP pin and RCS on the inductor side and is determined by:
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
The following guidelines are recommended for optimal performance of the ADP3422 and ADP3415 in a power converter. The circuitry is considered in three parts: the power switching circuitry, the output filter, and the control circuitry.
Placement Overview
I RPP RCS - VIM t D (OFF )RCS / L (12) 2I H where tD(OFF) is the turn-off delay time of the power converter, including delays through the ADP3422, ADP3415, and the external MOSFETs, and IH is a user-programmed current set by a resistor on the ADP3422's HYSSET pin, which sets the current that is hysteretically switched in and out of the RAMP pin. Assuming a turn-off delay of 50 ns and a hysteresis-setting current of 30 A, the calculated value of RA is 162 . RA =
To protect the converter, the hysteretic current limiting should be set. The current limit programming resistor, RCL, which connects between the CS- pin and the core output is given by:
kI RCS ( IO ( MAX ) + I RPP / 2) (13) 3I H where kI is a margin factor for the current limit setting. A typical value for kI might be 1.15, which would set the current limit point 15% above the maximum rated core current. Using the preceding design target values, a value of 441 for RCL is calculated. RCL =
1. For ideal component placement, the output filter capacitors will divide the power switching circuitry from the control section. As an approximate guideline, considered on a single-sided PCB, the best layout would have components aligned in the following order: ADP3415, MOSFETs and input capacitor, output inductor, current sense resistor, output capacitors, control components and ADP3422. Note that the ADP3422 and ADP3415 are completely separated for an ideal layout, which is only possible with a two-chip solution. This will minimize jitter in the control caused by having the driver and MOSFETs close to the control and give more freedom in the layout of the power switching circuitry. 2. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance--especially if the vias extend to the opposite side of the PCB where a plane can more readily transfer heat to air.
Power Switching Circuitry ADP3415, MOSFETs, and Input Capacitors
In order to optimize the power savings by always using the minimum allowed CPU supply voltage, the IMVP-2 specification introduces two operating-mode-dependent voltage shifts. The first shift is for optimizing the output voltage when the battery-optimized-mode (BOM) VID code is selected. The shift is achieved by connecting a resistor, RBSHIFT, between the BSHIFT pin and ground. The shift will be used whenever the BOM pin is driven low, indicating that the BOM VID code is selected. The shift is given by:
3. Locate the ADP3415 near the MOSFETs so the parasitic inductance in the gate drive traces and the trace to the SW pin is small, and so that the ground pins of the ADP3415 are closely connected to the lower MOSFET's source. 4. Locate at least one substantial (i.e., > ~10 F) input bypass MLC capacitor close to the MOSFETs so that the physical area of the loop enclosed in the electrical path through the bypass capacitor and around through the top and bottom MOSFETs (drain-source) is small. This is the switching power path loop. 5. Make provisions for thermal management of all the MOSFETs. Heavy copper and wide traces to ground and power planes will help to pull the heat out. Heat sinking by a metal tap soldered in the power plane near the MOSFETs will help. Even just small airflow can help tremendously. Paralleled MOSFETs will help spread the heat, even if the on-resistance is higher.
VBSHIFT =
RD - RA V 1+ RBSHIFT VID , BOM RC
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6. An external "antiparallel" schottky diode (across the bottom MOSFET) may help efficiency a small amount (< ~1 %); a MOSFET with a built in antiparallel schottky is more effective. For an external schottky, it should be placed next to the bottom MOSFET or it may not be effective at all. Also, a higher current rating (bigger device with lower voltage drop) is more effective. 7. The ground pin of the ADP3415 should be connected into the power switching circuitry ground plane, and the VCC bypass capacitor should be close to the VCC pin and connected into the same ground plane.
Output Filter Output Inductor and Capacitors, Current Sense Resistor
14. Absolutely avoid crossing any signal lines over the switching power path loop, described previously. 15. Accurate voltage positioning depends on accurate current sensing, so the control signals which monitor the voltage differentially across the current sense resistor should be kelvin connected. 16. The RC filter used for the current sense signal should be located near the control components.
Table I. VID Code
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
VVID 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 1.250 1.200 1.150 1.100 1.050 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 0.775 0.750 0.725 0.700 0.675 0.650 0.625 0.600
8. Locate the current sense resistor very near to the output capacitors. 9. PCB trace resistances from the current sense resistor to the output capacitors, and from the output capacitors to the load should be minimized, known (calculated or measured), and compensated for as part of the design if it is significant. (Remote sensing is not sufficient for relieving this requirement!) A square section of 1-ounce copper trace has a resistance of ~500 mW. Using 2~3 squares of copper can make a noticeable impact on a 15 A design. 10. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 11. The ground connection of the output capacitors should be close to the ground connection of the lower MOSFET and it should be a ground plane. Current may pulsate in this path if the power source ground is closer to the output capacitors than the power switching circuitry, so a close connection will minimize the voltage drop.
Control Circuitry ADP3422, Control Components
12. If the placement overview cannot be followed, then in order to avoid introducing ground noise from the power switching stage into the control circuitry, the ground pin of the ADP3422 should be Kelvin-connected into the ground plane near the output capacitors. All other control components should be grounded on that same signal ground. 13. If critical signal lines (i.e., signals from the current sense resistor leading back to the ADP3422) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier.
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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28)
0.386 (9.80) 0.378 (9.60)
28
15
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 14
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
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C01882-.8-10/01(0)
PRINTED IN U.S.A.

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